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國外電子與通信教材系列數(shù)字設(shè)計/Verilog HDL、VHDL和SystemVerilog實現(xiàn)(第六版)(英文版)
國外電子與通信教材系列數(shù)字設(shè)計/Verilog HDL、VHDL和SystemVerilog實現(xiàn)(第六版)(英文版) 版權(quán)信息
- ISBN：9787121395864
- 條形碼：9787121395864 ; 978-7-121-39586-4
- 裝幀：一般膠版紙
- 冊數(shù)：暫無
- 重量：暫無
- 所屬分類：>>
國外電子與通信教材系列數(shù)字設(shè)計/Verilog HDL、VHDL和SystemVerilog實現(xiàn)(第六版)(英文版) 本書特色
#例題豐富，推演詳盡。 #綜合了基本CMOS集成工藝和邏輯門。 #使用VHDL和SystemVerilog進行數(shù)字設(shè)計。 #例題豐富，推演詳盡。 #綜合了基本CMOS集成工藝和邏輯門。 #使用VHDL和SystemVerilog進行數(shù)字設(shè)計。
國外電子與通信教材系列數(shù)字設(shè)計/Verilog HDL、VHDL和SystemVerilog實現(xiàn)(第六版)(英文版) 內(nèi)容簡介
本書是一本系統(tǒng)介紹數(shù)字電路設(shè)計的很好教材，旨在教會讀者關(guān)于數(shù)字設(shè)計的基本概念和基本方法。全書共分10章，內(nèi)容涉及數(shù)字邏輯的基本理論，組合邏輯電路、時序邏輯電路、寄存器和計數(shù)器、存儲器與可編程邏輯器件，寄存器傳輸級設(shè)計、半導(dǎo)體和CMOS集成電路、標準IC和FPGA實驗、標準圖形符號、Verilog HDL、VHDL、SystemVerilog與數(shù)字系統(tǒng)設(shè)計等。全書結(jié)構(gòu)嚴謹，選材新穎，內(nèi)容深入淺出，緊密聯(lián)系實際，教輔資料齊全。
國外電子與通信教材系列數(shù)字設(shè)計/Verilog HDL、VHDL和SystemVerilog實現(xiàn)(第六版)(英文版) 目錄
Contents
1 Digit a l S ys tems and Binar y Numbers 17
1.1 Digital Systems 17
1.2 Binary Numbers 20
1.3 Number-Base Conversions 22
1.4 Octal and Hexadecimal Numbers 25
1.5 Complements of Numbers 27
1.6 Signed Binary Numbers 33
1.7 Binary Codes 38
1.8 Binary Storage and Registers 47
1.9 Binary Logic 50
2 Boolean Algebra and Logic Gate s 57
2.1 Introduction 58
2.2 Basic Definitions 58
2.3 Axiomatic Definition of Boolean Algebra 59
2.4 Basic Theorems and Properties of Boolean Algebra 63
2.5 Boolean Functions 66
2.6 Canonical and Standard Forms 72
2.7 Other Logic Operations 81
2.8 Digital Logic Gates 83
2.9 Integrated Circuits 89
3 Gate-Level Minimization 98
3.1 Introduction 99
3.2 The Map Method 99
3.3 Four-Variable K-Map 106
3.4 Product-of-Sums Simplification 111
3.5 Don’t-Care Conditions 115
3.6 NAND and NOR Implementation 118
3.7 Other Two-Level Implementations 126
3.8 Exclusive-OR Function 131
3.9 Hardware Description Languages (HDLs) 137
3.10 Truth Tables in HDLs 154
4 Combinational Logic 163
4.1 Introduction 164
4.2 Combinational Circuits 164
4.3 Analysis of Combinational Circuits 165
4.4 Design Procedure 169
4.5 Binary Adder–Subtractor 172
4.6 Decimal Adder 184
4.7 Binary Multiplier 186
4.8 Magnitude Comparator 188
4.9 Decoders 191
4.10 Encoders 195
4.11 Multiplexers 198
4.12 HDL Models of Combinational Circuits 205
4.13 Behavioral Modeling 231
4.14 Writing a Simple Testbench 239
4.15 Logic Simulation 245
5 Synchronous Sequential Logic 261
5.1 Introduction 262
5.2 Sequential Circuits 262
5.3 Storage Elements: Latches 264
5.4 Storage Elements: Flip-Flops 269
5.5 Analysis of Clocked Sequential Circuits 277
5.6 Synthesizable HDL Models of Sequential Circuits 291
5.7 State Reduction and Assignment 316
5.8 Design Procedure 321
6 Registers and Counters 342
6.1 Registers 342
6.2 Shift Registers 346
6.3 Ripple Counters 354
6.4 Synchronous Counters 359
6.5 Other Counters 367
6.6 HDL Models of Registers and Counters 372
7 Memory and Programmable Logic 393
7.1 Introduction 394
7.2 Random-Access Memory 395
7.3 Memory Decoding 402
7.4 Error Detection and Correction 407
7.5 Read-Only Memory 410
7.6 Programmable Logic Array 416
7.7 Programmable Array Logic 420
7.8 Sequential Programmable Devices 424
8 Design at the Registe r Transfer Leve l 445
8.1 Introduction 446
8.2 Register Transfer Level (RTL) Notation 446
8.3 RTL Descriptions 448
8.4 Algorithmic State Machines (ASMs) 466
8.5 Design Example (ASMD CHART) 475
8.6 HDL Description of Design Example 485
8.7 Sequential Binary Multiplier 503
8.8 Control Logic 508
8.9 HDL Description of Binary Multiplier 514
8.10 Design with Multiplexers 529
8.11 Race-Free Design (Software Race Conditions) 545
8.12 Latch-Free Design (Why Waste Silicon?) 548
8.13 SystemVerilog—An Introduction 549
9 Laborator y Experiments with
Standard ICs and FPGAs 571
9.1 Introduction to Experiments 571
9.2 Experiment 1: Binary and Decimal Numbers 576
9.3 Experiment 2: Digital Logic Gates 579
9.4 Experiment 3: Simplification of Boolean Functions 581
9.5 Experiment 4: Combinational Circuits 583
9.6 Experiment 5: Code Converters 584
9.7 Experiment 6: Design with Multiplexers 586
9.8 Experiment 7: Adders and Subtractors 588
9.9 Experiment 8: Flip-Flops 591
9.10 Experiment 9: Sequential Circuits 593
9.11 Experiment 10: Counters 595
9.12 Experiment 11: Shift Registers 596
9.13 Experiment 12: Serial Addition 600
9.14 Experiment 13: Memory Unit 601
9.15 Experiment 14: Lamp Handball 603
9.16 Experiment 15: Clock-Pulse Generator 607
9.17 Experiment 16: Parallel Adder and Accumulator 609
9.18 Experiment 17: Binary Multiplier 611
9.19 HDL Simulation Experiments and Rapid Prototyping with FPGAs 615
10 Standard Graphic Symbols 621
10.1 Rectangular-Shape Symbols 621
10.2 Qualifying Symbols 624
10.3 Dependency Notation 626
10.4 Symbols for Combinational Elements 628
10.5 Symbols for Flip-Flops 630
10.6 Symbols for Registers 632
10.7 Symbols for Counters 635
10.8 Symbol for RAM 637
Appendix 640
Answers to Selected Problems 654
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國外電子與通信教材系列數(shù)字設(shè)計/Verilog HDL、VHDL和SystemVerilog實現(xiàn)(第六版)(英文版) 作者簡介
M. Morris Mano，美國加利福尼亞州立大學電子和計算機工程系的教授，出版過多部有關(guān)數(shù)字邏輯、計算機設(shè)計基礎(chǔ)的教材；Michael D. Ciletti，美國科羅拉多大學教授。
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