1��introduction
��1.1 cad tool flows
1.1.1 custom vlsi and cell design flow
1.1.2 hierarchical cell/block asic flow
1.2 what this book is and isn't
1.3 bugs in the tools?
1.4 tool setup and execution scripts
1.5 typographical conventions
2��cadence dfii and icfb
��2.1 cadence design framework
��2.2 starting cadence
��2.3 summary
3��composer schematic capture
��3.1 starting cadence and making a new
��working library
��3.2 creating a new cell
3.2.1 creating the schematic view of a full adder
3.2.2 creating the symbol view of a full adder
3.2.3 creating a two-bit adder using the fulladder bit
��3.3 schematics that use transistors
��3.4 printing schematics
3.4.1 modifying postscript plot files
3.5 variable, pin, and cell naming restrictions
3.6 summary
4 verilog simulation
4.1 verflog simulation of composer schematics
��4.1.1 verilog-xl: simulating a schematic
4.1.2 nc_verilog: simulating a schematic
4.2 behavioral verilog code in composer
4.2.1 generating a behavioral view
4.2.2 simulating a behavioral view
4.3 stand-alone verilog simulation
4.3.1 verilog-xl
4.3.2 nc_verilog
4.3.3 vcs
4.4 timing in verilog simulations
4.4l behavioral versus transistor switch simulation
4.4.2 behavioral gate timing
4.4.3 standard delay format (sdf) timing
4.4.4 transistor timing
��4.5 summary
5��virtuoso layout editor
5.1 an inverter schematic
��5.1.1 starting cadence kfb
5.1.2 making an inverter schematic
5.1.3 making an inverter symbol
5.2 layout for an inverter
5.2.1 creating a new layout view
5.2.2 drawing an nmostransistor
5.2.3 drawing a pmos transistor
5.2.4 assembling the inverter from the transistor layouts
5.2.5 using hierarchy in layout
5.2.6 virtuoso command overview
������
6 standard cell design template
7 spectre analog simulator
8 cell characterization
9 verilog synthesis
10 abstract generation
11 soc encounter place and route
12 chip assembly
13 design example
a tool and setup scripts
b scripts to drive the tools
c technology and cell libraries
bibliography
index